1. Field of the Invention
The present invention generally relates to voltage regulator circuits/modules and, more particularly, to providing regulated voltage to loads at high current and low voltage with fast transient load response capability and circuits capable of doing so.
2. Description of the Prior Art
Many commercially available electronic devices require power at a well-regulated, substantially constant or well-defined voltage for proper operation. Among such devices, microprocessors and other high-speed logic circuits generally present loads which are most demanding to accommodate.
Current trends in designs for microprocessors have featured increased levels of integration of circuitry on a single chip and the use of higher clock speeds. These design trends have also led to lower (e.g. one volt or less) and more stringent and/or complex voltage regulation requirements (e.g. 10% or less, possibly with specified voltage droop with increasing current to reduce power dissipation requirements) at higher currents (e.g. 130 Amperes or more) and, particularly for programmed microprocessors, extremely high current slew rates (e.g. 20 A/nsec.). High efficiency is also demanded since many microprocessor applications derive power from batteries which can limit the time of operation before the batteries become excessively discharged. Small size and weight and low cost are also very desirable, particularly for use with microprocessors.
Many of these requirements and desirable features impose conflicting constraints on design or require trade-offs which may be very difficult to accommodate. For example, accommodation of high current slew rate can be achieved with large output filter capacitance but which may compromise accurate voltage control and increase size, weight and cost of the power supply. Similarly, the requirement for lower power supply output voltages generally compromises efficiency since a lower output voltage generally increases the voltage step-down which must be achieved by a DC to DC converter while very sophisticated power supply designs are required to achieve even very small increases in efficiency. On the other hand, some voltage converter or transformer designs are known which may be of characteristically very high efficiency but cannot achieve other desired characteristics while maintaining such efficiency or presenting intractable design problems.
In order to accommodate such conflicting requirements for power supply and voltage regulator circuits, a two-stage approach as shown in FIG. 1 has been proposed which is described in detail in U.S. patent application Ser. No. 11/691,800, filed Mar. 27, 2007, and which is hereby fully incorporated by reference. In this arrangement, a first unregulated step-down converter comprises a series connection of four switching transistors Q1-Q4 with capacitors C1-C3 respectively connected across adjacent pairs of transistors. When alternate transistors (e.g. Q1 and Q3 or Q2 and Q4) are switched on while the other alternate transistors are turned off and vice-versa, capacitor C2 is alternately connected in parallel with capacitor C1 or C3 of a capacitive voltage divider to provide for DC current to be drawn therefrom with low ripple voltage while providing very high efficiency of 97% to 98%. The second stage, in series with the first stage provides one or, preferably, more switching regulators in parallel and of differing phases to minimize ripple voltage and allow the use of a relatively small output capacitor. Any topology of the individual switching regulators may be used and this configuration is not limited to the buck regulators illustrated. Such a second stage receives a reduced voltage (e.g. 5-6 volts) input from the first step-down converter stage and thus can achieve increased efficiency, depending on switching frequency, compared to a regulator having a higher voltage (e.g. 12 volts) input. However, since the two stages are in series in this design, each stage must be designed to handle the full power load and thus efficiency is compromised during operation at low load which, for microprocessors in particular, can be a substantial fraction of the total operating time.
A proposal to reduce this compromise of efficiency is illustrated in FIG. 2. The basic principle of this proposed design is to provide a plurality of unregulated power supplies and a single regulated power supply in parallel such that the predominant portion of the power to the load is supplied by the high efficiency unregulated converters (each preferably operating as class-E inverter plus rectifier which achieves a high output impedance and thus functions as a current source) and regulating the output voltage while delivering only a small portion of the total power from the regulated cell which may comprise either a switched or linear regulator having a low output impedance in order to control the dynamics of the system. Since the regulated cell supplies only a very small portion of the total power at steady state, high efficiency requires that it be designed to deliver only low power. Consequently, the fully parallel power supply architecture of FIG. 2 cannot accommodate rapid load transients and high current slew rates which are typical of loads presented by microprocessors.
Thus, in summary, while many voltage regulator topologies are known and power supply architectures have become quite sophisticated, such designs are far from ideal for the types of loads presented by some current and foreseeable applications, particularly those including microprocessors. The effects of trade-offs necessary to accommodate the many demands of such applications are particularly severe and increasing in severity as present trends in integrated circuit designs continue. It can be foreseen that current power supply architectures and design approaches such as those shown in FIGS. 1 and 2 (neither of which is admitted to be prior art in regard to the present invention) will become unacceptable in the very near future.